Embodiments of the present disclosure relate generally to semiconductor integrated circuits and, more particularly, to internal voltage generation circuits.
In general, various internal voltages for operating the internal circuits of a semiconductor memory device are generated internally based on the external voltages, for example, a power supply voltage VDD and a ground voltage VSS. The internal voltages for operating the internal circuits of the semiconductor memory device include: a core voltage VCORE provided to a memory core region; a high voltage VPP used to drive or overdrive the word lines; and a back-bias voltage VBB provided to a bulk region (or a substrate) of the NMOS transistors in the memory core region.
The internal voltages to operate the internal circuits of the semiconductor memory device also include: a cell plate voltage VCP provided to a plate node of cell capacitors in the memory core region; and a bit line pre-charge voltage VBLP used to pre-charge the bit lines. The cell plate voltage VCP and the bit line pre-charge voltage VBLP may be generated from the core voltage VCORE and may be generated to have a half level of the core voltage VCORE for minimization of power consumption.
The cell plate voltage VCP and the bit line pre-charge voltage VBLP may be generated from a single internal voltage generation circuit. In the conventional internal voltage generation circuits, driving the internal voltage (e.g., the cell plate voltage VCP or the bit line pre-charge voltage VBLP) may be ended when the cell plate voltage VCP or the bit line pre-charge voltage VBLP has a half level of the core voltage VCORE. In contrast, the cell plate voltage VCP (or the bit line pre-charge voltage VBLP) may be driven when a level of the cell plate voltage VCP (or the bit line pre-charge voltage VBLP) is higher or lower than a half level of the core voltage VCORE. When the internal voltage (e.g., the cell plate voltage VCP or the bit line pre-charge voltage VBLP) is not driven, the internal voltage generation circuit may be referred to as being in a dead zone.
The conventional internal voltage generation circuits have been configured to compare an internal voltage (e.g., the cell plate voltage VCP or the bit line pre-charge voltage VBLP) with a plurality of reference voltages to drive the internal voltage. In such a case, when the internal voltage has a level between an upper reference voltage and a lower reference voltage, the conventional internal voltage generation circuits may be in a dead zone that the internal voltage is not driven.
A voltage difference between the upper and lower reference voltages may be reduced due to variations of some conditions, for example, processes, voltages and/or temperatures (PVT). If the voltage difference between the upper and lower reference voltages is reduced, a range of the dead zone may be narrowed to increase the power consumption of the internal voltage generation circuits.